The latest India Semiconductor Mission approvals add a SiC fab, advanced packaging, and high-volume assembly across Odisha, Andhra Pradesh, and Punjab. With ?4,600 crore in new investment and 2,034 skilled jobs—plus tariff headwinds—India must balance domestic demand and export pivots while it builds self-reliance.
New Delhi (ABC Live): The latest India Semiconductor Mission approvals—see the Cabinet note here—push India’s chip plan forward. However, “self-sufficiency” is not one endpoint. Instead, it spans wafer fabrication (mature and advanced nodes), assembly/packaging (2.5D/3D), power discretes (Si/SiC), memory, RF/analog, and the materials, tools, and talent behind them. Consequently, India’s near-term path leans on mature-node fabs, Si/SiC devices, and fast ATMP/OSAT scale-up. As a result, import dependence can fall this decade. Nevertheless, full autonomy in advanced logic and memory will take longer and will require deep technology partnerships, EUV tools, and more local inputs.
Why ABC Live is publishing this report
We aim to inform debate and also track delivery. Therefore, we will:
- monitor readiness, ramp, yield, and jobs across all India Semiconductor Mission approvals;
- test whether incentives become real output in SiC devices, advanced packaging, and mature-node logic;
- show how the build-out supports EVs, power, defence, telecom, and AI/HPC;
- follow how the 60,000+ trainees enter fabs, ATMPs, and suppliers;
- map depth in glass substrates, 3DHI, gases, and chemicals;
- guide MSMEs and investors in Odisha, Punjab, Andhra Pradesh, and Gujarat; and
- apply Punjab’s lessons so current projects avoid old traps.
Executive Summary
- New approvals (4): SiCSem (Odisha), 3D Glass Solutions (Odisha), ASIP (Andhra Pradesh), CDIL (Punjab) — confirmed by PIB here.
- Fresh investment: ~?4,600 crore (about ?1,150 crore per project)
- Direct skilled jobs: 2,034
- ISM total so far: 10 projects with ~?1.60 lakh crore across six states
- What’s new: India’s first commercial SiC fab plus a glass-substrate + 3DHI packaging hub
Project Details (what, where, and how much)
| Company | State | Focus | Annual Capacity (select) | Use Cases |
|---|---|---|---|---|
| SiCSem Pvt. Ltd. | Odisha (Info Valley, Bhubaneswar) | SiC fab + packaging | 60,000 SiC wafers; 96M packaged units | Defence, EVs/fast chargers, rail, data-centre racks, solar inverters, appliances |
| 3D Glass Solutions (3DGS) | Odisha (Info Valley, Bhubaneswar) | Advanced packaging + embedded glass | 69,600 glass panels; 50M assembled units; 13,200 3DHI modules | AI/HPC, photonics, co-packaged optics, RF/auto, defence |
| ASIP Technologies | Andhra Pradesh | System-in-Package (SiP) assembly | 96M assembled units | Mobile, set-top boxes, auto, consumer |
| Continental Device India (CDIL) | Punjab (Mohali) | Discrete semiconductors (Si & SiC) | 158.38M units (MOSFETs, IGBTs, Schottky diodes, transistors) | EVs/charging, renewables, power conversion, industrial/telecom |
Data Snapshot
Front-end and special tech
- SiC wafers: 60,000/year (SiCSem)
- Glass panels and 3DHI: 69,600 panels/year and 13,200 modules/year (3DGS)
Assembly and packaging scale
- Assembled units: ?304.38M/year (3DGS + ASIP + CDIL)
- Packaged units: 96.0M/year (SiCSem)
- Combined for share view (“assembled-like”): ?400.38M/year
Money and jobs (simple ratios)
- Avg. investment per new project: ~?1,150 crore
- Capital per direct job: ~?2.26 crore
- Investment per annual assembled-like unit: ~?115 (mix metric; not comparable to wafer capex or ASPs)
Where the volume sits (assembled-like share)
- Punjab (CDIL): ~39.6%
- Odisha (SiCSem + 3DGS): ~36.5%
- Andhra Pradesh (ASIP): ~24.0%
Why this mix helps
First, one front-end SiC fab plus three back-end sites speeds output. Next, SiC power devices match India’s push in EVs, rail, and clean power. Finally, glass-based substrates and 3DHI lift India toward AI/HPC-grade packaging.
Punjab’s Past, and the Takeaways for Today
What went wrong earlier
Punjab tried early at Mohali and faced a major fire, slow upgrades, and unclear control. Consequently, the site stayed on older tech for too long.
Guardrails for CDIL Mohali
- Make safety core: strong fire systems, cleanroom zones, dual power/water; quarterly third-party drills.
- Keep upgrades rolling: plan 18–24 months ahead for test, metrology, and reliability tools.
- Clear the path: one-window permits and land with public due dates.
- Spread supply risk: add second sources and keep buffers on site.
- Grow talent: build a power-devices academy; link promotions to uptime, yield, and quality.
Cluster impact
If these steps hold, CDIL’s high-power discretes can seed a robust Punjab power-electronics cluster.
Impact of the U.S.–India (Trump) Tariff War
What happened and when
On August 6, 2025, the U.S. announced an extra 25% tariff on Indian goods—on top of “reciprocal” tariffs—raising duties on some exports to ~50%. The move applies 21 days after August 7, unless talks change the terms. India, however, is still negotiating adjustments.
Who is most exposed
Government figures suggest about 55% of exports could be covered. Early reports say textiles and jewellery are hit hardest, while phones and pharma look less exposed. Even so, electronics exporters must still review U.S. lanes.
What this means for ISM projects
- Higher risk: OSAT/ATMP/SiP shipments to U.S. buyers face margin squeeze. Plants may pivot to EU/MEA/ASEAN or boost India-first demand.
- Lower risk: SiC power devices serving EVs, chargers, rail, renewables, defence can lean on domestic demand and non-U.S. markets.
- Policy valve: Because talks continue, sector carve-outs for semiconductor sub-assemblies remain possible.
Immediate playbook (practical steps)
- Lock domestic offtake with EV/charger, rail, solar, and grid OEMs.
- Run dual qualifications (U.S. and non-U.S.) and adjust price/mix swiftly.
- Push for carve-outs using data on jobs and value-add.
- Localize inputs faster—substrates, leadframes, passives, gases/chemicals.
- Watch KPIs: U.S. order share, ASP changes post-tariff, win–loss vs ASEAN, utilization, margin hold.
Two scenarios to prepare for
- Soft-landing: partial roll-backs or sector exemptions this quarter; modest margin trims.
- Prolonged frictions: tariffs last through year-end; U.S. volumes dip while domestic EV/power and non-U.S. markets backfill.
When Can India Rely More on Local Chips?
| Segment | What “self-reliant” looks like | Likely timeline |
|---|---|---|
| Power discretes (Si/SiC) | Local parts meet most EV/charger/industrial demand | 2027–2029 (approvals: PIB link) |
| Assembly/packaging (ATMP/OSAT) | Most electronics packaged/assembled in India | 2026–2028 (Micron ATMP in Gujarat: Micron link) |
| Mature-node logic (28–65 nm) | Local wafers for autos, PMICs, MCUs, DDI | 2027–2029 (Tata–PSMC/Dholera: PIB link) |
| Advanced packaging (3DHI/photonic) | Local AI/HPC modules at volume | Late-2027 onward |
| Advanced nodes (?7 nm) | Local wafers for phone APs and AI chips | Early-2030s+ |
| Memory (DRAM/NAND wafers) | Local wafer lines | 2030s (packaging earlier via Micron ATMP) |
Bottom line: by 2028–2030, India can cut imports sharply in power, ATMP/OSAT, and mature logic. Nevertheless, full freedom in advanced logic and memory remains a 2030s goal.
Risks and How to Reduce Them
- Ramp and yield: track first-pass yield and uptime; keep spares; embed vendor engineers.
- Permits and land: one-window clearances with public trackers; clear escalation steps.
- Supply shocks: multi-source inputs; vendor parks near plants; strategic stocks.
- People and skills: place 60,000+ trainees into fabs and suppliers; add short SiC and packaging courses.
- Market swings: diversify end-use across EV/power, AI/HPC, telecom, industrial.
What to Watch Next (6–18 months)
- SiCSem (Odisha): wafer ramp/month, first-pass yield, first SiC shipments
- 3DGS (Odisha): glass-panel qualification, 3DHI reliability, AI/HPC orders
- ASIP (Andhra Pradesh): SiP line use, cycle time, customer qualifications
- CDIL (Punjab): MOSFET/IGBT/Schottky mix, reliability tests, EV/renewable wins
Conclusion
The newest India Semiconductor Mission approvals add SiC making, advanced packaging, and high-volume assembly where India needs them most. Consequently, with 10 active projects, a large training pipeline, and a stronger design base, India is moving toward a reliable, export-ready chip chain. Ultimately, that supports Atmanirbhar Bharat while giving global buyers another stable source.
Sources
-
PIB (?4,600 crore approvals): https://www.pib.gov.in/PressReleasePage.aspx?PRID=2155456
-
PIB/Make in India (Tata–PSMC roadmap): https://www.pib.gov.in/PressReleasePage.aspx?PRID=2115171
-
Micron (Gujarat ATMP): https://investors.micron.com/news-releases/news-release-details/micron-announces-new-semiconductor-assembly-and-test-facility
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